Semiconductor fabrication typically requires fabricating multiple layers on a structure in which some or all of the layers include patterned features. Overlay metrology is the measurement of the relative positions of structures on various layers of a sample, which are critical to the performance of a fabricated device and must typically be controlled within tight tolerances. For example, overlay metrology may measure the relative positions of features on different sample layers as a measure of the layer-by-layer alignment of fabrication tools.
Not all device feature layouts are amenable to direct overlay measurements. Further, overlay measurements may damage or otherwise affect the performance of device features. Accordingly, overlay measurements are commonly performed on dedicated overlay targets having features designed for sensitive overlay measurements rather than directly on device features. However, differences in size, orientation, density, and/or location on the sample of overlay targets relative to the device features may introduce a mismatch between measured overlay at the target and actual overlay of device features. For example, features on different layers of overlay targets are commonly spatially separated to avoid overlap and facilitate measurements of features on buried layers. However, open areas associated with spatially separated features may not be compatible with microelectronics fabrication. Further, device features commonly include stacked structures such that overlay measurements of spatially separated features may introduce measurement errors.
Accordingly, ensuring device-relevant overlay measurements on overlay targets remains an ongoing challenge in overlay metrology.